Gated Precharging: Using Temporal Locality of Subarrays to Save Deep-Submicron Cache Energy

نویسنده

  • Se-Hyun Yang
چکیده

Modern high-performance cache implementations use subarrays to reduce the capacitive load on the bitlines and achieve faster access time [6]. To overlap bitline precharging time with address decoding and wordline assertion, caches typically precharge all subarrays simultaneously prior to a cache access. Though only a small number of subarrays are accessed on a cache access, precharging all subarrays leads high energy consumption in modern and future high-performance deep-sub micron caches, because current CMOS scaling trends significantly increase the leakage from bitlines as process generation evolves [2, 3].

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

منابع مشابه

Power - Aware High - Performance Cache Memory

iii Acknowledgements iv Abstract CMOS technology scaling in recent decades has enabled a phenomenal performance improvement in microprocessors by allowing designers to increase the level of integration at higher clock frequencies. Unfortunately, technology scaling has also created unprecedented design challenges, including, but not limited to, the devices' leakage current, the interconnect dela...

متن کامل

Performance and Energy Trade-offs of Bitline Isolation in Nanoscale CMOS Caches

High-performance cache architectures always pull up the bitlines in all cache subarrays to hide the bitline charging latency prior to a cache access. Unfortunately, such architectures lead to significant bitline discharge in unaccessed subarrays in nanoscale CMOS caches and waste power. Recent proposals advocate bitline isolation to reduce bitline discharge in unaccessed subarrays by turning of...

متن کامل

Exploiting Choice in Resizable Cache Design to Optimize Deep-Submicron Processor Energy-Delay

Cache memories account for a significant fraction of a chip’s overall energy dissipation. Recent research advocates using “resizable” caches to exploit cache requirement variability in applications to reduce cache size and eliminate energy dissipation in the cache’s unused sections with minimal impact on performance. Current proposals for resizable caches fundamentally vary in two design aspect...

متن کامل

Specializing Cache Structures for High Performance and Energy Conservation in Embedded Systems

Increasingly tight energy design goals require processor architects to rethink the organizational structure of microarchitectural resources. We examine a new multilateral cache organization, replacing a conventional data cache with a set of smaller region caches that significantly reduces energy consumption with little performance impact. This is achieved by tailoring the cache resources to the...

متن کامل

An Integrated Circuit/Architecture Approach to Reducing Leakage in Deep-Submicron High-Performance I-Caches

Deep-submicron CMOS designs maintain high transistor switching speeds by scaling down the supply voltage and proportionately reducing the transistor threshold voltage. Lowering the threshold voltage increases leakage energy dissipation due to subthreshold leakage current even when the transistor is not switching. Estimates suggest a five-fold increase in leakage energy in every future generatio...

متن کامل

ذخیره در منابع من


  با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

عنوان ژورنال:

دوره   شماره 

صفحات  -

تاریخ انتشار 2002